The IPC High-Reliability Forum for Mil-Aero and Automotive Sectors


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I had the pleasure of attending IPC’s High Reliability Forum (HRF) in Baltimore in May. As the IPC scripted it, it was a “Technical Conference with a Focus on Electronics Subjected to Harsh-Use Environments.”

HRF included a half-day tutorial on “Achieving Improved Reliability with Failure Analysis” taught by Bhanu Sood, commodity risk assessment engineer, NASA Goddard Space Flight Center.

Michael Carano, the forum moderator, opened HRF at 9 am. Attendance topped 80, with pre-registration at over 90. Michael introduced the keynote speaker for the forum, American Standard Circuits CEO Anaya Vardya, whose keynote highlighted the North American overview of the PCB industry’s challenges. Specific points included:

  • Pricing erosion
  • Higher technology
  • Cost of doing business
  • Demanding customers
  • Competition
  • Hiring the right people

The growth of China as a PCB manufacturing center has eroded North America’s PCB facilities from a high of over 1,000 in 2000 to the most current (2016) count of 255. Of those, only six had revenues of over $50M USD and most were under $6M (~150). The total of $5.4B worth of shipments were distributed into seven major markets.

Anaya used his own company’s philosophy and milestones to highlight their approach to people, equipment, software, product capabilities, demanding customers and competition. He concluded with a summary of the key “Global Strategy” for success.

The second presentation was by J.R. Strickland and Jerry Magera of Motorola Solutions: “How MSI Applied Technology Beat the Microvia Hidden Threat.” This was a summary and report on their research into stacked-microvia failures that were escaping into products. This report was the main substance of the recently released IPC White Paper, IPC-WP-023 “IPC Technology Solutions White Paper on Performance-Based Printed Board OEM Acceptance—Via Chain Continuity Reflow Test: The Hidden Reliability Threat—Weak Microvia Interface.” 

Starting in 2010, stacked microvias begin exhibiting field failures and steps were taken to understand why. The product failures were intermittent in nature but more often at hot temperatures. This led to their unpredictable reliability. Existing quality controls and reliability testing was not showing up these defects. Various experiments were conducted to find a fool-proof method of quality control. By 2011, an in-situ reflow test of six passes through the SMT reflow oven while instrumented with a 4-wire Kelvin resistance circuit was finalized and contained the problem. The problem was a weak microvia interface to the prior plated copper on stacked vias. Communication and consulting with industry colleges indicated they were having similar problems. All new microvia designs were to use staggered microvia chains until the root cause was thoroughly understood. A board coupon was established of the microvia chain and this proved to be effective to screen each board before assembly. IPC TM650 2.6.27A was released in September 2017 as a standard for this Pb-free reflow oven acceptance test. MSI has had zero product failures since implementation. The reflow coupon consists of six daisy chains to test each board:

  • S1 chain of staggered microvias
  • SX2 chain of stacked microvias
  • S3 smallest finished hole size PTH via
  • S4 & S5 daisy chain of constructed of via features used in the corresponding PWB
  • S6 FHS of greatest number of PTH, PIH component via

They concluded with promises to share their data as they search for the root cause of this microvia problem, as stacked microvias are inevitable in future high-reliability designs. Additional work is needed by industry to identify root cause and implement corrective actions.

The third presentation, “HDI Microvia Reliability for any Temperature Extreme,” was presented by Kevin Knadle of I3 Electronics. Kevin, formerly of IBM, gave an excellent history of PTH reliability testing at IBM and the use of current induced thermal cycle (CITC) testing. Covered as IPCTM-650 2.6.26 Method B, this small, single-net coupon of 100 vias is only 1.75” x 0.3” and designed by IBM to be used many times on a panel and easily adapted to in-line process monitoring. The test uses current to heat the coupon at three degrees per second to 245°C for a dwell time of 40 seconds and repeats the cycle for 200-700 cycles per day. The temperature coefficient of resistance (TCR) is measured continuously and used to determine the coupon’s temperature. A 4-wire resistance bridge monitors the via daisy chain.

To read the full version of this article which originally appeared in the August 2018 issue of PCB007 Magazine, click here.

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