Beyond Design: Alternative Series Termination Techniques

In a previous column on “Transmission Line Terminations,” I discussed the three most common termination strategies: series, end, and differential. These techniques are used to eliminate impedance mismatch and hence reflections to avoid crosstalk and electromagnetic radiation. As a general rule, transmission line (trace) termination is necessary when the round trip propagation time of the signal is equal to or greater than the transition (rise or fall) time of the driver; otherwise, there will be data errors caused by signal degradation. In this month’s column, I will elaborate on two particular cases of series termination that every PCB designer will come across.
1. Distributing a Clock to Multiple Loads
The objective of the clock is to provide circuit timing and thereby coordinate the activity within the system. With memory circuits, the clock pulse will trigger the input and output of data, and therefore, must be timed such that each bit of data arrives and stabilizes before the next clock cycle. To do this means that both the clock and data lines must be routed to exact delays within the specified setup and hold times. Since digital signals cannot be sped up, the only option is to add length to the line to delay the signal arrival to match the arrival speed of the longest lines in the bus. However, the clock signal should always be the longest delay of all so that the data signals have time to settle before they are clocked.

Routing clock signals to multiple loads can be done in many ways. A buffer could be used for each individual receiver, or the use of a dedicated clock driver incorporating a phase-locked loop (PPL) to synchronize the timing is also a common solution. However, this adds to the cost and consumes precious real estate. 

Star routing is ideal for distributing a clock to multiple loads in low- to medium-speed designs. The routing fans out from the driver through a series resistor for each load. This reduces reflections. The delay for each leg is then matched for each load. For clock lines with multiple receivers, it is best to route to the receiver that is the farthest from the driver first, and then match that delay when routing to the other receivers.

Clock signals generally have a fast rise time and hence are noisy due to high harmonic content; as a result, they must be isolated from the rest of the circuitry. To reduce the impact of a noisy clock circuit, it is good practice to locate the clock circuitry in the center of the PCB and star route out to the loads in precise patterns and at a specific delay.

The electromagnetic fields surrounding a microstrip (outer layer) trace exist partially within the dielectric material(s) and partially within the surrounding air. Since air has a dielectric constant of one, which is always lower than that of FR-4 and solder mask (typically 4.3 and 3.3, respectively), mixing a little air into the equation will lower the effective dielectric constant and speed up the signal propagation. Even if the trace widths are adjusted on each layer, as the impedance is identical, the propagation speed of microstrip is always faster than stripline—typically by 13–17%. 

The speed of propagation of digital signals is independent of trace geometry and impedance but reliant on the dielectric constant of the materials. Therefore, if a signal changes layers in the stackup, then the delay will also vary. If you are aware of this issue, then the trace delays (Figure 1) can be matched to compensate for the varying flight time so that at the nominal temperature, all signals running on either microstrip or stripline will arrive at the receiver simultaneously. PCB designers should always match delays—not length.


Before starting placement and routing, detailed interconnect routing constraints should be established. These constraints—based on pre-layout simulation, manufacturing restrictions, and IC manufacturer’s recommendations and guidelines—will control the placement and routing processes. Online design rule checks (DRCs) will warn the designer when a constraint is violated.

On a multilayer PCB, clock signals should be routed on a stripline (inner layer) sandwiched between two solid reference planes to reduce radiation. The spacing between the signal trace and the return planes should be as small as possible to increase coupling and reduce the loop area.
The three constraints to keep in mind include:

  1. Route clock signals between the planes, fanout out close to the driver (200 mils) dropping to an inner layer, and route back up to the load again with a short fanout. A series terminator is required for each load.
  2. Use the same reference plane (GND if possible) for the return signal, as this reduces the loop area and hence radiation.
  3. Minimize crosstalk to other signals by keeping a distance of at least three times the trace width to sensitive signals.

2. Bi-Directional Data Termination
With series termination, the resistor needs to be close to the source (Figure 2). This ensures that the reflected pulse sees the internal driver source impedance and the resistor in series (usually totaling 50 ohms). Since this matches the transmission line, it completely absorbs the reflected energy. However, data flows in both directions from the CPU to the memory, when writing to memory, then back from the memory to the CPU for reading the memory data. Where do we place the series terminator in a point-to-point configuration—at one end of the data-trace, or maybe in the center?


Out of habit—or perhaps for fear of doing the wrong thing—one would usually put the termination close to the CPU rather than the load. The simulated waveforms of the impact of having a termination resistor close to the driver, close to the load, and also in the middle of the transmission line show little distinction. However, there is a better unconventional solution: placing a termination resistor at each end of the transmission line (Figure 3). Figure 4 presents an improved eye diagram using this solution for both the read/write cycles. The blue waveform is the termination at both ends—the red and green waveforms are at either end of the transmission line.


Having a resistor at both ends of the transmission line, close to the driver and load, is an elegant solution as the resistor and input capacitance of the tri-state load basically form an AC termination reducing reflections.

On-die termination (ODT) is implemented with several combinations of resistors on the later versions of DDR memory. Designers can use a combination of transistors which have different values of turn-on resistance. In the case of DDR2, there are three kinds of internal resistors: 150-ohm, 75-ohm, and 50-ohm. The internal on-die termination values in DDR3 are 120 ohms, 60 ohms, 40 ohms, and so forth. But for devices that do not incorporate ODT, dual-series terminations suffice.
Key Points

  • The three most common termination  
strategies are series, end, and differential.
  • Transmission line termination is necessary when the round-trip propagation time of the signal is equal to or greater than the transition (rise or fall) time of the driver.
  • The objective of the clock is to provide circuit timing and thereby coordinate the activity within the system.
  • For clock lines with multiple receivers,  
it is best to route to the receiver that is the farthest away from the driver first, and then match that delay when routing to  
the other receivers.
  • The clock signal should have the longest delay of all so that the data signals have time to settle before they are clocked.
  • Star routing is ideal for distributing a clock to multiple loads in low- to medium-speed designs.
  • Clock signals generally have a fast rise time and hence are noisy due to high harmonic content; as a result, they must be isolated from the rest of the circuitry.
  • The propagation speed of microstrip is always faster than stripline.
  • The speed of propagation of digital signals is independent of trace geometry and impedance.
  • PCB designers should always match delays—not length.
  • Clock signals should be routed on a stripline (inner layer) sandwiched between two solid reference planes to reduce radiation.
  • Placing a resistor at both ends of the transmission line, close to the driver and load, is an elegant solution to terminate a bi-directional signal.  

Further Reading

  1. B. Olney, “Beyond Design: Transmission Line Termination,” Design007 Magazine, March 2020.
  2. B. Olney, “Beyond Design: The 10 Fundamental Rules of HSD Part 4,” Design007 Magazine, December 2018.
  3. B. Olney, “Beyond Design: Signal Flight Time Variance in Multilayer PCBs,” The PCB Design Magazine, December 2017.
  4. B. Olney, “Beyond Design: Effective Routing of Multiple Loads,” The PCB Design Magazine, February 2014.
  5. Cadence Design Systems, “Contamination Delay in Clock Circuits: Best PCB Routing Techniques,” February 24, 2020.
  6. H. W. Johnson & M. Graham, High-Speed Digital Design: A Handbook of Black Magic, Prentice-Hall, 1993.

This column originally appeared in the July 2020 issue of Design007 Magazine.



Beyond Design: Alternative Series Termination Techniques


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Beyond Design: Transmission Line - From Barbed Wire to High-speed Interconnect


Contrary to common belief, the transmission line does not carry the signal itself but rather guides electromagnetic energy from one point to another. It is the movement of the electromagnetic field or energy, not voltage or current that transfers the signal. The voltage and current exist in the conductor, but only as a consequence of the field being present as it moves past.

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Mythbusting: There are No One-way Trips!


One of the greatest myths in PCB design is that we only have to route signal traces from pin-to-pin to make a complete connection. And, that ensuring these traces have matched delay is the only timing issue we need to consider. However, current is not a one way trip--it must complete the circuit back to the source to provide the round-trip current loop.

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Matched Length Does Not Always Equal Matched Delay


In previous columns, Columnist Barry Olney has discussed matched length routing and how matched length does not necessarily mean matched delay. But, all design rules, specified by chip manufacturers regarding high-speed routing, specify matched length--not matched delay. In this month's column he takes a look at the actual differences between the two.

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Beat the Traffic Jam - Effective Routing of Multiple Loads


In a previous column, Barry Olney discussed various termination strategies and concluded that a series terminator is best for high-speed transmission lines. But, what if there are a number of loads--how should these transmission lines be routed? For perfect transfer of energy and to eliminate reflections, the impedance of the source must equal the impedance of the trace(s) to the load.

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PDN Planning and Capacitor Selection, Part 2


In Part 1 of this column, Barry Olney looked closely at how to choose the right capacitor to lower the AC impedance of the power distribution network (PDN) at a particular frequency. This month he continues from there looking at the one-capacitor-value-per-decade and optimized value approaches.

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Beyond Design: Entanglement - The Holy Grail of High-Speed Design


While high-speed SERDES serial communications seems to currently be at the cutting edge of technology, maybe it will shortly become an antiquated low-speed solution--even speed-of-light fiber optics may become obsolete. This month, Columnist Barry Olney looks at how quantum physics is transforming our world and how it could affect PCB design.

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Beyond Design: Impedance Matching: Terminations


The impedance of the trace is extremely important, as any mismatch along the transmission path will result in a reduction in signal quality and possibly the radiation of noise. Mismatched impedance causes signals to reflect back and forth along the lines, which causes ringing at the load.

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Material Selection for SERDES Design


Many challenges face the engineer and PCB designer working with new technologies. For SERDES--high-speed serial links--loss, in the transmission lines, is a major cause of signal integrity issues. Reducing that loss, in its many forms, is not just a matter of reducing jitter, bit error rate (BER) or inter-symbol interference (ISI).

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Beyond Design: Practical Signal Integrity


"If you are a digital designer, you will eventually have SI problems whether you like it or not. But all is not lost. If you learn to work with these issues, then you will soon become proficient with high-speed design," says columnist Barry Olney.

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Beyond Design: Design for Profit


Design for profit (DFP) is gaining more recognition as it becomes clear that the cost reduction of printed circuit assemblies cannot be controlled by manufacturing engineers alone. The PCB designer now plays a critical role in cost reduction, says columnist Barry Olney.

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Beyond Design: Skewed Again


Differential skew has become a performance limiting issue for high-speed SERDES links. The operation of such links involves significant amounts of signal processing to recover clocks, reduce the effects of high-frequency losses, reduce inter symbol interference, and improve signal-to-noise ratio.

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Beyond Design: Losing a Bit of Memory


No matter what type of memory used in a design, the clock should always have the longest delay. This ensures that the other signals have time to settle before the clock arrives at the device and samples the bus.

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Beyond Design: Electromagnetic Fields, Part 2


In his last column, Barry Olney discussed how magnetic fields revolve around the earth and how these fields are also present in a multilayer board. Part 2 of "Electromagnetic Fields" will look at how the phenomena influence transmission lines and how they can be applied in a BEM field solver.

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Beyond Design: Electromagnetic Fields, Part 1


Our whole world literally revolves around electromagnetic fields. Columnist Barry Olney says much insight into high-speed PCB design can be gained by understanding the behavior of transmission lines and the influence of their associated electromagnetic fields.

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Beyond Design: Postmortem Simulation


Developing the practice of performing a post-mortem analysis on every project facilitates a culture of continuous improvement. This embedded culture of ongoing, positive change is the best way to ensure long-term success according to Barry Olney.

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Beyond Design: Mixed Digital-Analog Technologies


The key to a successful mixed digital-analog design is functional partitioning, understanding the current return path, routing control and management, and using a common ground plane. Barry Olney takes us into the mix this week.

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Beyond Design: Pre-Layout Simulation


Pre-layout simulation allows a designer to identify and eliminate signal integrity, crosstalk and EMC issues early in the design process. This is the most cost-effective way to design a board. Barry Olney explains why in this case, sooner is better than later.

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Beyond Design: Power Distribution Network Planning


The power distribution network (PDN) of a multilayer PCB should distribute low noise and stable power to ICs over the entire board area. Ideally, the AC impedance, between power and ground, should be zero, up to the maximum operating frequency for reliable performance.

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Intro to Board-Level Simulation and the PCB Design Process


Board-level simulation reduces costs by identifying potential problems at the conceptual stage, so that they can easily be avoided, and then catching any further issues during the design process, eliminating the potentially disastrous final-stage changes. By Barry Olney.

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Board-Level Simulation and the Design Process: Plan B - Post-Layout Simulation


Post-layout simulation covers batch mode simulation, which automatically scans nets on an entire PCB, flagging signal integrity, crosstalk and EMC hot spots. While post-layout simulation can be used for disaster recovery, ideally this process is completed during the design process. Barry Olney explains.

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Beyond Design: A New Slant on Matched-Length Routing


This month, Barry Olney discusses the traditional serpentine routing for matched length signals and looks at a potentially desirable alternative, the octagonal spiral pattern, that can be especially useful if real estate is at a premium.

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Beyond Design: Controlling the Beast


In this column, we will tackle the "microstripum crosstalkus radiarta," an insidious little creature more commonly known as microstrip crosstalk radiation. Thriving on the outer layers of PCBs, crosstalk, like fleas on a dog, can't be eliminated completely or forever; the key is learning how to minimize and control it.

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Beyond Design: Embedded Signal Routing


Is radiation actually attenuated when high-speed signals are routed embedded between the planes? There are specific constraints and factors to consider when assessing just how much attenuation we actually get from embedding the high-speed signals between the planes. Barry Olney breaks it all down.

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Beyond Design: The Dumping Ground


By definition, a ground plane in a PCB is a layer of copper that appears to most signals as an infinite ground potential. This month, we discuss best practices for selecting reference planes and routing pairs for high-speed designs on multilayer boards.

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Beyond Design: Controlling Emissions and Improving EMC


Unintended noise can be a formidable enemy, and it is best to totally eliminate, control or attenuate the emissions at the source. Controlling the impedance of the substrate and terminating the transmission line to match the impedance of the respective source and load significantly reduces radiated noise, virtually eliminating the noise at the source.

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PCB Design Techniques for DDR, DDR2 & DDR3, Part 2


This second and final part in a series examining PCB design techniques will look at a comparison of DDR2 and DDR3, DDR3 design guidelines, pre-layout analysis, critical placement, design rules, and post-layout analysis.

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